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1 ? fn6168.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL88550A synchronous step down controller with sourcing and sinkin g ldo regulator ISL88550A integrates a synchronous buck pwm controller to generate vddq, a sourcing and sinking ldo linear regulator to generate vtt, and a 10ma reference output buffer to generate vttr. the buck controller drives two external n-channel mosfets to generate output voltages down to 0.7v from a 2v to 25v input with output currents up to 15a. the ldo can source up to 2.5a and sink up to -2.0a continuously. both the ldo output and the 10ma reference buffer output can be made to track the refin voltage via a built-in resistive divider. these features make the ISL88550A ideally suited for ddr memory applications in desktops, notebooks and graphics cards. the pwm controller in the ISL88550A uses constant-on-time pwm architecture with a programmable switching frequency of up to 600khz. this control scheme handles wide input/output voltage ratios with ease and provides 100ns ?instant-on? response to load transients while maintaining high efficiency and a relatively constant switching frequency. the ISL88550A offers full programmable uvp/ovp and skip mode options ideal in portable applications. skip mode allows for improved efficiency at lighter loads. the vtt and vttr outputs track to vrefin/2. the high bandwidth of this ldo regulato r allows excellent transient response without the need for bul k capacitors, thus reducing the cost and size. the buck controller and ldo regulators are provided with independent current limits. adju stable loss-less fold-back current limit for the buck regulat or is achieved by monitoring the drain-to-source voltage drop of the low side synchronous mosfet. once over-current is removed, the regulator is allowed to enter soft-start again. this helps minimize power dissipation during short-circuit condition. additionally, over- voltage and under-voltage prot ection mechanisms are built in. the ISL88550A allow flexible sequencing and standby power management using s hdna#, and stby# inputs. features ? pb-free plus anneal available (rohs compliant) buck controller ? constant-on pwm with 100ns load-step response ? start-up with pre-biased output voltage ? up to 95% efficiency ? 2v to 25v input voltage range ? 1.8v/2.5v fixed or 0.7v to 3.5v adjustable output ? 200khz/300khz/450khz/600khz switching frequencies ? programmable current limit with foldback capability ? 1.7ms digital soft-start and independent shutdown ? overvoltage/undervoltage protection option ? power-good window comparator ldo section ? fully integrated vtt and vttr capability ? vtt has + 2.5a/-2.0a sourcing/sinking capability ? start-up with pre-biased output voltage ? vtt and vttr outputs track vrefin/2 ? vtt & vttr 1% of vrefin/2 ? low all-ceramic outp ut capacitor designs ? 1.0v to 2.8v input refin range ? analog soft-start option and independent shutdown ? power-good window comparator applications ? ddr, ddr ii, and ddr iii memory power supplies ? desktop computers ? notebooks and desknotes ? graphics cards ? game consoles ? networking and raid ordering information part number part marking temp range (c) package pkg. dwg. # ISL88550Airz (see note) ISL88550Airz -40 to +85 28 ld 55 thin qfn (pb-free) l28.5x5b ISL88550Airz-t (see note) ISL88550Airz -40 to +85 28 ld 55 thin qfn tape and reel (pb-free) l28.5x5b note: intersil pb-free plus anneal products em ploy special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet october 12, 2005
2 fn6168.0 october 12, 2005 pinout ISL88550A (28 ld tqfn) top view ss vtts vttr pgnd2 vtt vtti refin tpo shdna# avdd skip# gnd pgnd1 vdd fb out vin ugate phase boot lgate 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 stby# pok2 pok1 ilim ref ovp/uvp ton ISL88550A
3 fn6168.0 october 12, 2005 absolute maximum rati ngs thermal information vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +25v vdd, avdd, vtti to gnd. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v shdna#, refin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v ss, pok1, pok2, skip#, ilim, fb to gnd . . . . . . . . . . -0.3v to 6v stby#, t on , ref, uvp/ovp to gnd. . . . . . . .-0.3v to av dd +0.3v out, vttr to gnd . . . . . . . . . . . . . . . . . . . . . .-0.3v to av dd +0.3v lgate to pgnd1 . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v ugate to phase . . . . . . . . . . . . . . . . . . . . -0.3v to vboot +0.3v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v phase to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to +33v vtt to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vtti+0.3v vtts to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to av dd +0.3v pgnd1, pgnd2 to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3v ref short circuit to gnd. . . . . . . . . . . . . . . . . . . . . . . . . continuous thermal resistance ja (c/w) jc (c/w) tqfn package (notes 1, 2). . . . . . . . . 31 1.5 operating conditions junction temperature range. . . . . . . . . . . . . . . . . .-55c to +150c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65c + 150c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the "case temp" location is the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications vin = +15v, v dd = av dd = shdna# = stby# = boot = ilim = 5v, out = refin = vtti = 2.5v, fb = skip# = ovp/uvp = gnd. pgnd1 = pg nd2 = phase = gnd, vtts = vtt, t on = open, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c (note 3) note: following are target specifications. final limits may change as a result of characterization. parameter conditions min typ max unit main pwm controller v in input voltage range 225v v dd , av dd input voltage range 4.5 5.5 v output adjust range 0.7 3.5 v output voltage accuracy (note 4) fb = out 0.693 0.7 0.707 v fb = gnd 2.470 2.5 2.53 v fb = v dd 1.78 1.8 1.82 v soft-start ramp time rising edge of shdna# to full current limit 1.7 ms on-time v in = 15v, v out = 1.5v (note 5) t on = gnd (600khz) 170 194 219 ns t on = ref (450khz) 213 243 273 ns t on = open (300khz) 316 352 389 ns t on = av dd (200khz) 461 516 571 ns minimum, off-time (note 5) 200 300 450 ns v in quiescent supply current 25 40 a v in shutdown supply current shdna# = stby# = gnd 1 5 a combined av dd and v dd quiescent supply current all on (pwm, vtt, & vttr on), v fb = 0.75v 2.5 5 ma stby# = gnd (only vttr & pwm on), v fb = 0.75v 1 2 ma combined av dd and v dd shutdown supply current shdna# = stby# = gnd 2 10 a av dd undervoltage lockout threshold rising edge of av dd 4.1 4.25 4.4 v hysteresis 50 mv reference reference voltage av dd = 4.5v to 5.5v; i ref = 0 to 130a 1.98 2 2.02 v ISL88550A
4 fn6168.0 october 12, 2005 reference load regulation i ref = 0 to 50a 0.01 v ref under-voltage lockout v ref rising 1.93 v hysteresis 300 mv fault detection ovp trip threshold (referenced to nominal v out ) uvp/ovp = av dd 110 114 118 % uvp trip level referred to nominal v out 65 70 75 % pok1 trip level referred to nominal v out lower level, falling edge, 1% hysteresis 87 90 93 % upper level, rising edge, 1% hysteresis 107 110 113 % pok2 trip level referred to nominal vtts and vttr lower level, falling edge, 1% hysteresis 87.5 90 92.5 % upper level, rising edge, 1% hysteresis 107.5 110 112.5 % pok2 disable threshold (measured at refin) v refin rising (hysteresis = 75mv typical) 0.7 0.9 v uvp blanking time from rising edge of shdna# 8 14 25 ms ovp, uvp, pok_ propagation delay 10 s pok_ output low voltage i sink = 4ma 0.3 v pok_ leakage current v pok_ = 5.5v, vfb = 0.8v, vtts = 1.3v 1 a ilim adjustment range 0.25 2.00 v ilim input leakage current 0.1 a current limit threshold (fixed) pgnd1 to phase ilim = av dd 45 50 55 mv current limit threshold (adjustable) pgnd1 to phase v ilim = 2v 170 200 235 mv current-limit threshold (negative direction) pgnd1 to phase skip# = av dd -75 -60 -45 mv current-limit threshold (negative direction) pgnd1 to phase skip# = av dd, ilim = 2v -250 mv current-limit threshold (zero crossing) pgnd1 to phase 3mv thermal shutdown threshold rising 150 c hysteresis 15 internal boot diode v d forward voltage pvcc-v boot , i f = 10ma 0.60 0.70 v i boot_leakage leakage current v boot = 25v, phase = 20v, pvcc = 5v 300 500 na mosfet drivers ugate gate driver on-resistance v boot -v phase = 5v 1.5 5 ? lgate gate driver on-resistance in high state 1.5 5 ? lgate gate driver on-resistance in low state 0.6 3 ? dead time (additional to adaptive delay) lgate rising 30 ns ugate rising 30 electrical specifications vin = +15v, v dd = av dd = shdna# = stby# = boot = ilim = 5v, out = refin = vtti = 2.5v, fb = skip# = ovp/uvp = gnd. pgnd1 = pg nd2 = phase = gnd, vtts = vtt, t on = open, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c (note 3) (continued) note: following are target specifications. final limits may change as a result of characterization. parameter conditions min typ max unit ISL88550A
5 fn6168.0 october 12, 2005 inputs and outputs logic input threshold high (shdna#, skip#, stby# ) rising edge 1.2 1.7 2.20 v hysteresis 225 mv logic input current (shdna#, skip#, stby#) -1 1 a fb input logic levels low (2.5v output) 0.1 v high (1.8v output) 2.1 v input bias current (fb) -0.1 0.1 a four-level input logic levels (t on , ovp/uvp) high av dd -0.4 v floating 3.15 3.85 ref 1.65 2.35 low 0.5 logic input current (t on , ovp/uvp, note 4) -3 +3 a out input resistance fb = gnd 125 250 500 k ? fb = av dd 90 180 270 k ? fb adjustable mode 125 250 500 k ? out discharge mode on-resistance 15 30 ? linear regulators (vttr and vtt) vtti input voltage range 1.0 2.8 v vtti supply current i vtt = i vttr = 0 0.1 1 ma vtti shutdown current shdna# = stby# = gnd 10 a refin input impedance v refin = 2.5v 17 20 27 k ? refin range 1.0 2.8 v vtt, vttr uvlo threshold (measured at out) 0.01 0.1 0.2 v soft-start charge current v ss = 0 4 a vtt internal mosfet high-side on- resistance i vtt = -100ma, v vtti = 1.5v, av dd = 4.5v (t j = 125c) 0.10 0.28 ? vtt internal mosfet low-side on- resistance i vtt = 100ma, av dd = 4.5v (t j = 125c) 0.18 0.43 ? vtt output accuracy (referenced to vttr) v refin = 1.8v or 2.5v, i vtt = 5ma -1.5 1.5 % vtt load regulation v refin = 2.5v, i vtt = 0 to 1.5a 1 % v refin = 1.8v, i vtt = 0 to 1.5a 1 % vtt positive current limit vtt = 0 2.5 3.0 4.0 a vtt negative current limit vtt = vtti -3.5 -2.5 -2.0 a vtts input current v vtts = 1.5v, vtt open 0.1 1 a vttr output error (referenced to v refin /2) v refin = 1.8v, i vttr = 0 ma -1.25 1.25 % vttr current limit vttr = 0 or vtti 20 40 60 ma electrical specifications vin = +15v, v dd = av dd = shdna# = stby# = boot = ilim = 5v, out = refin = vtti = 2.5v, fb = skip# = ovp/uvp = gnd. pgnd1 = pg nd2 = phase = gnd, vtts = vtt, t on = open, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c (note 3) (continued) note: following are target specifications. final limits may change as a result of characterization. parameter conditions min typ max unit ISL88550A
6 fn6168.0 october 12, 2005 notes: 3. specifications to -40c are guarant eed by design, not production tested. 4. when the inductor is in continuous conduc tion, the output voltage will have a dc regulat ion level higher than the error compa rator threshold by 50% of the ripple. in discontinuous conduction, the output voltage will have a dc regulation level higher than the trip level b y approximately 1.5% due to slope compensation. 5. on-time and off-time specifications ar e measured from 50% point to 50% point at the ugate pin with phase = gnd, v boot = 5v, and a 250pf capacitor connected from ugate to phase. actual in-circu it times may differ due to mosfet switching speeds. electrical specifications vin = +15v, v dd = av dd = shdna# = stby# = boot = ilim = 5v, out = refin = vtti = 2.5v, fb = skip# = ovp/uvp = gnd. pgnd1 = pg nd2 = phase = gnd, vtts = vtt, t on = open, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c (note 3) (continued) note: following are target specifications. final limits may change as a result of characterization. parameter conditions min typ max unit pin descriptions pin name function 1tont on on-time selection-control input. this four-level logic input sets the nominal ugate on-time. connect to gnd, ref, av dd , or leave t on unconnected to select the follow ing nominal switching frequencies: t on = av dd (200khz) t on =open (300khz) t on = ref (450khz) t on = gnd (600khz) 2 ovp/uvp overvoltage/undervoltage protection control input. th is four-level logic input enables or disables the overvoltage and/or undervoltage protection. the overvoltage limit is 116% of the nominal output voltage. the undervoltage limit is 70% of the nominal output voltage. discharge mode is enabled when ovp is also enabled. connect the ovp/uvp pin to the following pins for the desired function: ovp/uvp = av dd (enable ovp and discharge mode, enable uvp) ovp/uvp = open (enable ovp and discharge mode, disable uvp) ovp/uvp = ref (disable ovp and discharge mode, enable uvp) ovp/uvp = gnd (disable ovp and discharge mode, disable uvp) 3 ref +2.0v reference voltage output. bypass to gnd with a 0.1f (min) bypass capacitor. ref can supply 50a for external loads. can be used for setting voltage for ilim. ref turns off when shdna#, stby# are low. 4 ilim current-limit threshold adjustment for buck regulator. the current-limit threshold across pgnd and phase is 0.1 times the voltage at ilim. connect ilim to a resistive-divider (typical ly from ref) to set the current-limit threshold between 25mv and 200mv (with 0.25v to 2v at ilim). connect to av dd to select the 50mv default current-limit threshold. 5 pok1 buck power-good open-drain output. pok1 is lo w when the buck output voltage is more than 10% above or below the normal regulation point or during soft-s tart. pok1 is high impedance when the output is in regulation and the soft-start circuit has terminated. pok1 is low in shutdown. 6 pok2 ldo power-good open-drain output. in normal mode, pok2 is low when either vttr or vtts is more than 10% above or below the normal regulation point, wh ich is typically refin/2. in standby mode, pok2 responds only to vttr input. pok2 is low in shutdown, and when vrefin is less than 0.8v. 7 stby# stand-by pin. tie to low for low quiescent m ode where the vtt output is disabled with high impedance but the vttr buffer is kept alive if shdna# is high. po k2 takes input from only vttr in this mode. vtt is discharged to 0v when shdna# = gnd. pwm output can be on or off depending on the state of shdna#. 8 ss soft-start control pin for vtt & vttr. connect a capaci tor (c9 in typical applicat ion circuit) from ss to ground (see soft-start capacitor selection). leave ss open to disable soft-start. ss discharged to gnd when shdna# = gnd 9 vtts sensing pin for termination supply output. normally ti ed to vtt pin to allow accurate regulation to ? the refin voltage. connected to a resistor divider from vtt to gnd to regulate vtt to higher than ? the refin voltage. 10 vttr termination reference voltage. vttr tracks the value of the vtt output. 11 pgnd2 power ground for the vtt and vttr. 12 vtt termination power supply output. tie vtt to vtts to regulate to v refin /2. 13 vtti power supply input voltage for vtt. normally ti ed to output of buck regulator for ddr application. ISL88550A
7 fn6168.0 october 12, 2005 14 refin external reference input. this is us ed to regulate the vtt and vttr outputs to v refin /2 15 fb feedback input for buck output. connect to av dd for a +1.8v fixed output or to gnd for a +2.5v fixed output. for an adjustable output (0.7v to 5.5v), connect fb to a resistive-divider from the output voltage. fb regulates to +0.7v. 16 out output voltage sense connection. connect directly to the positive terminal of the buck capacitors. out senses the output voltage to determine the on-time fo r the high-side switching mosfet (q1 in the typical application circuit). out also se rves as the buck output?s feedbac k input in fixed-output modes. when discharge mode is enabled by ovp/uvp, the output capacitor is discharged through an internal 20 ? resistor connected between out and ground. 17 vin input voltage sense connection. connect to input power source. v in is used only to set the pwm on-time one-shot timer. this pin can range from 2v to 25v. 18 ugate high-side gate-driver output. swings from phase to boot. ugate is low when in shutdown or uvlo. 19 phase external inductor connection. connect phase to t he input side of the inductor. phase is used for both current limit and the return supply of the ugate driver. 20 boot boost flying-capacitor connection. connect to an external capacitor according to the typical application circuit (figure 27). see boost-suppl y diode and capacitor selection (boot). 21 lgate synchronous rectifier gate-driver output. swings from pgnd to v dd . 22 vdd supply input for the lgate gate drive. connect to +4.5v to +5.5v system supply voltage. bypass to pgnd1 with a 4.7f ceramic capacitor. 23 pgnd1 power ground for buck controller. connect pg nd1 externally to the underside of the exposed pad. 24 gnd analog ground for both buck and ldo. connect externally to the underside of the exposed pad. 25 skip# pulse-skipping control input. connect to av dd for low-noise, forced-pwm mode. connect to gnd to enable pulse-skipping operation. 26 avdd analog supply for both buck and ldo. bypass to gnd with a 1.0f ceramic capacitor. a 10 ? internal resistor is connected between v dd and av dd 27 shdna# shutdown control input a. use to control buck output. a rising edge on shdna# clears the overvoltage and undervoltage protection fault latches (see table 2 and table 3). connect av dd for normal operation. 28 tp0 test pin. must be connected to gnd externally pin descriptions (continued) pin name function typical operating characteristics vin = 12v, vddq = 1.8v, ton = gnd, skip# = avdd, circuit of figure 28, t a = 25c, unless otherwise noted. figure 1. efficiency vs load - 1.8v (t on = gnd) figure 2. switching frequency vs load (ton = gnd) 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load (a) efficiency (%) 3v in -skip 12v in -skip 25v in -skip 3v in -pwm 12v in -pwm 25v in -pwm 0.001 0.01 0.1 1 10 load (a) 0 100 200 300 400 500 600 700 frequency (khz) 3v in -skip 12v in -pwm 25v in -pwm 3v in -pwm 12v in -skip 25v in -skip ISL88550A
8 fn6168.0 october 12, 2005 figure 3. switching freq uency vs input voltage (t on = gnd) figure 4. switching frequency vs temperature (t on = gnd) figure 5. vddq regulation vs load - 1.8v fi gure 6. vddq output vs input voltage - 1.8v figure 7. output ripple vs load - 1.8v (t on = gnd) figure 8. vtt regulation vs vtt load typical operating characteristics (continued) vin = 12v, vddq = 1.8v, ton = gnd, skip# = avdd, circuit of figure 28, t a = 25c, unless otherwise noted. 400 425 450 475 500 525 550 575 600 625 650 675 700 4 6 8 101214161820222426 v in (v) frequency (khz) i out = 0a i out = 12a 450 470 490 510 530 550 570 590 -40 -30 -20 -10 0 10 20 30 40 50 70 80 90 100 temperature (c) frequency (khz) 60 i out = 12a i out = 0a 0.001 0.01 0.1 1 10 load (a) 1.775 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 vddq (v) 3v in -pwm 3v in -skip 12v in -pwm 12v in -skip 25v in -pwm 25v in -skip 1.775 1.780 1.785 1.790 1.795 1.800 4 6 8 10 12 14 16 18 20 22 24 26 v in (v) vddq (v) i out = 0a i out = 12a 0.001 0.01 0.1 1 10 load (a) 0 10 20 30 40 50 60 output ripple (mv) 3v in -pwm 3v in -skip 12v in -pwm 12v in -skip 25v in -pwm 25v in -skip 0.850 0.860 0.870 0.880 0.890 0.900 0.910 0.920 0.930 0.940 0.950 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 load (a) vtt (v) ISL88550A
9 fn6168.0 october 12, 2005 figure 9. vttr regulation vs vttr load figure 10. load transient (vddq) figure 11. load transient (vtt -1.5a to 1.5a) figure 12. power-up waveforms figure 13. power-down waveforms figure 14. vddq startup and shutdown into heavy load, discharge disabled typical operating characteristics (continued) vin = 12v, vddq = 1.8v, ton = gnd, skip# = avdd, circuit of figure 28, t a = 25c, unless otherwise noted. 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 load (a) vttr (mv) -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 vddq 100mv/div vtt 100mv/div vttr 100mv/div ivddq 10a/div 20s/div i vtt =1.5a, i vttr =15ma 10a 0a i vddq =12a, i vttr =15ma 20s/div vddq 100mv/div vtt 100mv/div vttr 100mv/div ivtt 2a/div 100s/div vddq 1v/div vtt 1v/div vttr 1v/div vin 10v/div v dd =5v, i vddq =12a, i vtt =1.5a, ivttr=15ma 100s/div vddq 1v/div vtt 1v/div vttr 1v/div vin 10v/div v dd =5v, i vddq =12a, i vtt =1.5a, ivttr=15ma 1ms/div vddq 1v/div vtt 500mv/div pok1 5v/div shdna# 5v/div i vddq =12a, i vtt =1.5a ISL88550A
10 fn6168.0 october 12, 2005 figure 15. vddq startup and shutdown into light load, discharge enabled figure 16. vtt, vttr startup and shutdown figure 17. overvoltage and turn-off of buck output figure 18. short circuit and recovery of vddq figure 19. short circuit and recovery of vddq figure 20. short circuit and recovery of vtt typical operating characteristics (continued) vin = 12v, vddq = 1.8v, ton = gnd, skip# = avdd, circuit of figure 28, t a = 25c, unless otherwise noted. 2ms/div vddq 1v/div vtt 500mv/div pok1 5v/div shdna# 5v/div r vddq =10 ? , r vtt =20 ? 200s/div vtt 500mv/div vttr 500mv/div pok2 1v/div stby# 5v/div i vtt =1.5a, i vttr =15ma 50s/div ugate 2v/div vddq 500mv/div lgate 2v/div vtt 500mv/div 100s/div vddq 1v/div ivddq 10a/div vin 10v/div iin 5a/div uvp disable, foldback current limit 50s/div vddq 1v/div ivddq 10a/div vin 10v/div iin 5a/div uvp enable 100s/div vtt 500mv/div ivtt 2a/div ISL88550A
11 fn6168.0 october 12, 2005 figure 21. functional block diagram on time compute trig 1-shot t on q trig 1-shot t off q + - intref intref 1.16 x quad level decoder blank ovp/uvp latch + - + - vdd-1v 1.0v phase phase zero crossing buck on/off bias vtt on/off vttr on/off + - 20msec timer por 0.7 x intref + - + - intref+10% interef-10% n fb decoder vout=1.8v vout=2.5v discharge logic vdd 2v reference intref + - + - intref/2+10% interef/2-10% + - + - intref/2+10% interef/2-10% n + - out 0.1v power down n + - + - n n vdd vdd current limit refin/2 out pgnd2 vtt ilim vin lgate pgnd1 ilim out skip# avdd gnd ref vtts refin vtti vtt pgnd2 vttr ss pok2 fb pok1 stby# shdna# ovp/uvp ton s r q s r q + - shutdown decoder 10 10k 10k boot ugate phase vdd + + on/off ISL88550A
12 fn6168.0 october 12, 2005 detailed description the ISL88550A combines a synchronous buck pwm controller, an ldo linear regulator, and a 10ma reference output. the buck controller drives two external n-channel mosfets to deliver load currents up to 15a and generates voltages down to 0.7v from a +2v to +25v input. the ldo linear regulator can source up to 2.5a and sink up to -2.0a continuously. these features make the ISL88550A ideally suited for ddr memory application. the ISL88550A buck regulator is equipped with a fixed switching frequency up to 600khz constant on-time pwm architecture. this control scheme handles wide input/output voltage ratios with ease, and provides 100ns ?instant-on? response to load transients while maintaining high efficiency with relatively constant switching frequency. the buck controller, ldo, and buffered reference output are provided with independent current limits. lossless fold-back current limit in the buck regulat or is achieved by monitoring the drain to source voltage drop of the low side fet. the ilim input is used to adjust this current limit. over-voltage protection is achieved by latching the low side synchronous fet on and the high side fet off when the output voltage is over 116% of its set output. it also features an optional under voltage protection by latching the mosfet drivers to the off state during an over current condition when the output voltage is lower than 70% of the regulated output. once the over current condition is removed, the regulator is allowed to soft-start again. this helps minimize power dissipation during a short circuit condition. the current limit in the ldo and buffered reference output is +3.0a/-2.5a and 40ma respectively and neither have the over or under voltage protection. when the current limit in either output is reached, the output no longer regulates the voltage, but will regulate the current to the value of the current limit. +5v bias supply (v dd and av dd ) the ISL88550A requires an external +5v bias supply in addition to the input voltage (v in ). keeping the bias supply external to the ic improves the efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and the gate drivers. v dd , av dd and v in can be connected together if the input source is a fixed +4.5v to +5.5v supply. v dd is the supply input for the buck regulator?s mosfet drivers, and av dd supplies the power for the rest of the ic. the current from the av dd and v dd power supply must supply the current for the ic and the gate drive for the mosfet?s. this maximim curre nt can be estimated as: where i vdd , + i avdd are the quiescent supply currents into v dd and av dd and q g1 and q g2 are the total gate charges of mosfets q1 and q2, (at v gs = 5v), in the typical application circuit and ? sw is the switching frequency. free-running constant-on-time pwm the constant on-time pwm control architecture is a pseudo fixed frequency, constant on-time, current-mode regulator with voltage feed forward (figure 21). this architecture relies on the output filter capacitor?s esr to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to the output voltage. another one-shot sets a minimum off time of 300ns typically. the on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley curr ent-limit threshold, and the minimum off-time one-shot has timed out. on-time one shot (t on ) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one- shot includes circuitry that vari es the on-time in response to input and output voltages. the high-side switch on-time is inversely proportional to the input voltage (v in ) and is proportional to the output voltage: where k (the on time scale factor) is set by the t on input connection (table 1) and r ds(on)q2 is the on-resistance of the synchronous rectifier (q2) in the typical application circuit. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: 1. the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band. 2. the inductor ripple-current operating point remains relatively constant, resulting in an easy design methodology and predictable output voltage ripple. the on-time one-shot has good accuracy at the operating points specified in the electrical characteristics table (approximately 12.5% at 6 00khz and 450khz and 10% at 200khz and 300khz). on-times at operating points far removed from the conditions specified in the electrical characteristics table can vary over a wider range. for example, the 600khz setting typically runs approximately 10% slower with inputs much greater than 5v due to the very short on-times required. the constant on-time translates only roughly to a constant switching frequency. the on-times guaranteed in the electrical characteristics table are influenced by resistive losses and by switching delays in the high-side mosfet. resistive losses, which include the inductor, both mosfets, the output capacitors esr, and any pc board copper losses () 2 g 1 g sw avdd vdd bias q q x f i i i + + + = () ( ) in 2 q on ds load out on v r i v k t + = ISL88550A
13 fn6168.0 october 12, 2005 in the output and ground, tend to raise the switching frequency as the load increases. the dead-time effect increases the effective on-t ime, reducing the switching frequency as one or both dead times are added to the effective on-time. the dead time occurs only in pwm mode, (skip# = v dd ), and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor?s emf causes phase to go high earlier than normal, extending the on-time by a period equal to the ugate-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including the synchronous rectifier, the inductor, and any pc board resistances; v drop2 is the sum of the resistan ces in the charging path, including the high-side switch (q1 in typical application circuit), the inductor, and any pc board resistances, and t on is the one-shot on-time (s ee section on on-time one- shot (t on ). automatic pulse-skipping mode (skip# = gnd) in skip mode, (skip# = gnd), an inherent automatic switchover to pfm takes place at light loads (figure 22). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current?s zero crossing. the zero-crossing comparator differentially senses the inductor current across the synchronous rectifier mosfet (q2 in typical application circuit). once v pgnd - phase drops below 5% of the current-limit threshold, (3mv for the default 50mv current-limit threshold), the comparator forces lgate low (see block diagram figure 21). this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor- current operation (also known as the critical conduction point). the load-current leve l at which pfm/pwm crossover occurs, i load(skip) , is equal to one-half the peak-to-peak ripple current, which is a functi on of the inductor value (see figure 22). this threshold is relatively constant, with only a minor dependence on the input voltage (v in ). where k is the on-time scale factor (see table 1). for example, in the typical appl ications circuit (k = 1.7s, v out = 2.5v, v in = 12v, and l = 1h), the pulse-skipping switchover occurs at: the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by selection of inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance rema ins fixed), and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. dc output accuracy specifications refer to the threshold of the error comparator. when the inductor is in continuous conduction, the ISL88550A regulates the valley of the output ripple, so the actual dc output vo ltage is higher than the trip level by 50% of the output ripple voltage. in discontinuous conduction (skip# = gnd and i load < i load(skip) ), the output voltage has a dc regulation level higher than the error comparator threshold by approximately 1.5% due to slope compensation. figure 22. pulse skipping/discontinuous crossover point () 2 drop in on 1 drop out sw v v t v v f + + = () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = in out in out skip load v v v l 2 k v i a 68 . 1 v 12 v 5 . 2 v 12 h 1 2 s 7 . 1 v 5 . 2 = ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? on-time 0time i peak l v in -v out ? i t = inductor current i load =i peak /2 on-time 0time i peak l v in -v out ? i t = inductor current i load =i peak /2 ISL88550A
14 fn6168.0 october 12, 2005 force pwm mode (skip# = av dd ) the low-noise forced-pwm mode, (skip# = av dd ), disables the zero-crossing comparator, which controls the low-side switch on-time. this forces t he low-side gate drive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while ugate maintains a duty factor of v out /v in . forced- pwm mode keeps the switching frequency fairly constant. however, forced-pwm operation comes at a cost where the no-load v dd bias current remains between 2ma and 20ma due to the external mosfets gate charge and switching frequency. forced-pwm mode is most useful for reducing audio frequency noise, improv ing load-transient response, and providing sink current capability for dynamic output voltage adjustment. current limit buck regulator (ilim) valley current limit the current-limit circ uit for the buck regulator portion of the ISL88550A employs a unique ?valley? current sensing algorithm that senses the voltage drop across phase and pgnd1 and uses the on-resistance of the rectifying mosfet (q2 in the typical application circuit) as the current sensing element. if the magnitude of the current sense signal is above the valle y current-limit threshold, the pwm controller is not allowed to initiate a new cycle (figure 24). with valley current limit sensing, the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor cu rrent ripple. therefore, the exact current limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and input voltage. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance . in forced-pwm mode, the ISL88550A also implements a negative current limit to preven t excessive reverse inductor currents when the buck regulator output is sinking current. the negative current-limit threshold is set to approximately 120% of the positive current limit and tra cks the positive current limit when v ilim is adjusted. th e current-limit threshold is adjusted with an external resistor-divider at ilim. a 2a to 20a divider current is recommended for accuracy and noise immunity. the current-limit threshold adjus tment range is from 25mv to 200mv. in the adjustable mode, the current limit threshold voltage (from phase to pgnd1) is precisely 1/10th the voltage seen at ilim. the threshold defaults to 50mv when ilim is connected to av dd . the logic threshold for switchover to the 50mv default value is approximately av dd - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the differential current-sense signals seen between phase and pgnd1. table 1. approximate k-factor errors t on setting typical k factor (s) k-factor error (10%) minimum v in at v out = 2.5v (h = 1.5, see dropout performance section) typical application comments 200khz (t on = av dd ) 5.0 10 3.15 4-cell li+ notebook use for absolute best efficiency 300khz (t on = open) 3.3 10 3.47 4-cell li+ notebook considered mainstream by current standards 450khz (t on = ref) 2.2 12.5 4.13 3-cell li+ notebook useful in 3 cell systems for lighter loads 600khz (t on = gnd) 1.7 12.5 5.61 +5v input good operating point for compound buck designs or desktop circuts. ISL88550A
15 fn6168.0 october 12, 2005 figure 23. adjustable current limit threshold figure 24. valley current-limit threshold por, uvlo, and soft-start internal power-on reset (por) occurs when av dd rises above approximately 2v, resetting the fault latch and the soft-start counter, powering up the reference, and preparing the buck regulator for operation. until av dd reaches 4.25v (typical), av dd undervoltage lockout (uvlo) circuitry inhibits switching. the controller inhibits switching by pulling ugate low and holding lgate low when ovp and shutdown discharge are disabled (ovp/uvp = ref or gnd) or forcing lgate high when ovp and shutdown discharge are enabled (ovp/uvp = av dd or open). see table 3 for detailed truth table for ovp/uvp and shutdown settings. when av dd rises above 4.25v, the c ontroller activates the buck regulator and initializes the internal soft start. the buck regulator?s internal soft-start allows a gradual increase of the current limit level during startup to reduce the input surge currents. the ISL88550A divides the soft-start period into five phases. during the first phase, the controller limits the current limit to only 20% of the full current limit. if the output does not reach regulation within 425s, soft start enters the second phase, and the current limit is increased by another 20%. this process repeats until the maximum current limit is reached, afte r 1.7ms, or when the output reaches the nominal regulation voltage, whichever occurs first. adding a capacitor in pa rallel with the external ilim resistors creates a continuously adjustable analog soft-start function for the buck regulator?s output. for most applications, ldo soft start is not necessary because of output charging current is limited to approximately 3.0a. for 20f ldo output capacitors, the minimum rise time is about 30s. however, soft start in the ldo section can be realized by tying a capacitor between the ss pin and ground. when stby# is driven low, or during thermal shutdown of the ldo?s, the ss capacitor is discharged. when stby# is driven high or when the thermal limit is removed, an internal 4a (typ) current charges the ss capacitor. the resulting linear ramp voltage on ss linearly increases the current-lim it comparator thresholds to both the vtt and vttr outputs, until full current limit is attained when ss reaches approximately 1.6v. this lowering of the current limit during start-up limits the initial in-rush current peaks, particularly when driving higher output capacitances. for good tracking, choose the value of the ss cap less than 390pf. leave ss floating to disable the soft- start feature. power ok (pok1) pok1 is an open-drain output for a window comparator that continuously monitors v out . pok1 is actively held low when shdna# is low and during the buck regulator outputs soft- start. after the digital soft-s tart terminates, pok1 becomes high impedance as long as the output voltage is within 10% of the nominal regulation voltage set by fb. when v out + - + - vdd-1v 1.0v lx ilim ISL88550A ref 9r r r a r b c ilim c ref i limit i load i peak inductor current i load(max) ? i i lim val () i load ? i 2 ----- ? = ISL88550A
16 fn6168.0 october 12, 2005 drops 10% below or rises 10% above the nominal regulation voltage, the ISL88550A pulls pok1 low. any fault condition forces pok1 low until the fault latch is cleared by toggling shdna# or cycling av dd power below 1v. for logic level output voltages, connect an exte rnal pull up resistor between pok1 and av dd . a 100k resistor works well in most applications. note that th e pok1 window detector is completely independent of the overvoltage and undervoltage protection fault detectors and the state of vtts and vttr. shdna# and out put discharge the shdna# input corresponds to the buck regulator and places the buck regulator?s portion of the ic in a low power mode (see electrical characteristics table). shdna# is also used to reset a fault signal such as an overvoltage or undervoltage fault. when output discharge is enabled (ovp/uvp = av dd or open) and shdna# is pulled low, or if uvp is enabled (ovp/uvp = av dd ) and v out falls to 70% of its regulation set point, the ISL88550A discharges the buck regulator output (via the out input) through an internal 15 ? switch to ground. while the output is di scharging, the pwm controller is disabled, but the reference remains active to provide an accurate threshold. when output discharge is disabled (ovp/uvp = ref or gnd), the controller does not actively discharge the buck output. under these conditions, the buck output discharge rate is determined by the load current and its output capacitance. the buck regulator detects and latches the discharge mode state set by ovp/uvp setting on startup. stby# the stby# input is an active low input that is used to shutdown only the vtt output. when stby# is low, vtt is high impedance, but the vttr output is still active if shdna# is high. vtt and vttr are pulled to 0v when shdna is low. power ok (pok2) pok2 is the open-drain output for a window comparator that continuously monitors the vt ts input and vttr output. pok2 is high impedance as long as the output voltage is within 10% of the nominal regulation voltage as set by refin. when v vtts or v vttr rise 10% above or 10% below their nominal regulation voltage, the ISL88550A pulls pok2 low. for logic level output voltages, connect an external pull up resistor between pok2 and av dd . a 100k resistor works well in most a pplications. note that the pok2 window detector is completely independent of the overvoltage and undervoltage pr otection fault detectors and the state of vddq. current limit (ldo for vtt and vttr buffer) the vtt output is a linear regu lator that regulates the input (vtti) to ? the v refin voltage. the feedback point for vtt is at the vtts input (see figure 21 block diagram). vtt is capable of sourcing up to 2.5a and sinking up to -2.0a continuously. the current limit for vtt and vttr is typically +3.0a/-2.5a and 40ma respectively. when the current limit for either output is reached, the outputs regulate the current not the voltage. the current limits for both vtt and vttr can be reduced from their full va lues by forcing the voltage at the ss pin below 1.6v (typ), or by tying a resistor rss between the ss pin and ground such that 4a*rss is less than 1.6v. pok2 is pulled low when refin is < 0.8v. fault protection the ISL88550A provides overvoltage/undervoltage fault protection in the buck controller. select ovp/uvp to enable and disable fault protection as shown in table 3. once activated, the contro ller continuously monitors the output for undervoltage and overvoltage fault conditions. any vddq shutdown due to ovp, uvp, otp or shdna# = 0 should also discharge vtt to 0v. ? overvoltage protection (ovp) when the output voltage rises above 114% of the nominal regulation voltage and ovp is enabled (ovp/uvp = av dd or open), the ovp circuit sets the fault latch, shuts down the pwm controller, and immediately pulls ugate low and forces lgate high. this turns on the synchronous rectifier mosfet with 1 00% duty cycl e, rapidly discharging the output capacitor and clamping the output to ground. note that immediately latching lgate high can cause the output voltage to go slightly negative due to energy stored in the output lc circuit at the instant the ovp occurs. if the load cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse polarity clamp. toggle shdna# or cycle av dd power below 1v to clear the fault latch and restart the controller. ovp is disabled when ovp/uvp is connected to ref or gnd (see table 3). ovp only applies to the buck output. the vtt and vttr outputs do not have overvoltage protection. when v ddq is discharged to 0v due to ovp, vtt is also discharged to 0v. table 2. shutdown and standby control logic shdna# stby# buck output vtt vttr gnd x off off (discharge to 0v) off (tracking ? refin) av dd gnd on off (high impedance) on av dd av dd on on on ISL88550A
17 fn6168.0 october 12, 2005 ? undervoltage protection (uvp) when the output voltage drops below 70% of its regulation voltage, and uvp is enabled (ovp/uvp = av dd or ref), the controller sets the fault latch and begins the discharge mode (see the shutdown and ou tput discharge section). uvp is ignored for 14ms (minimu m), after startup or after a rising edge on shdna#. toggle shdna# or cycle av dd power below 1v to clear the fault latch and restart the controller. uvp is disabled when ovp/uvp is left open or connected to gnd (see table 3). uvp only applies to the buck output. the vtt and vt tr outputs do not have under voltage protection. when vddq is discharged to 0v due to uvp, vtt is also discharged to 0v. ? thermal fault protection the ISL88550A features a therma l fault protection circuit, which monitors the buck regu lator of the ic, the linear regulator (vtt) and the buffered output (vttr). when the junction temperature of the ISL88550A rises above +150c, a thermal sensor acti vates the fault latch, pulls pok1 low, and shuts down the buck converter using discharge mode regardless of the ovp/uvp setting, and vtt is also discharged to 0v. toggle shdna# or cycle av dd power below 1v to reactivate the controller after the junction temperature cools by 15c. design procedure firmly establish the input voltage range (v in ) and maximum load current in the buck regulator before choosing a switching frequency and inductor operating point (ripple- current ratio or lir). the primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: ? input voltage range. the maximum value (vin (max)) must accommodate the worst-case, high ac adapter voltage. the minimum value (vin (min)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice, lower input voltages result in better efficiency. ? maximum load current. there are two values to consider. the peak load current (i peak ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current- limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing components. ? switching frequency. this choice dete rmines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses proportional to frequency and vin 2 . the optimum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical. ? inductor operating point. this choice provides trade- offs: size vs. efficiency and transient response vs. output ripple. low inductor values provide better transient response and smaller physical si ze but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to operat e at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum lo ad). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping (skip# = low at light loads), the inductor value also determines the load current value at which pfm/pwm switch over occurs. setting the output voltage (buck) preset output voltages the ISL88550A allows the selection of common voltages without requiring external components (figure 25). connect fb to gnd for a fixed 2.5v output, to av dd for a fixed 1.8v output, or connect fb directly to out for a fixed 0.7v output. table 3. ovp/uvp fault protection ovp/uvp discharge uvp protection ovp protection av dd 15 ? internal switch on ugate/lgate is low when shdna# = low for normal shutdown enabled. enabled. ugate pulled low and lgate forced high if ovp detected open 15 ? internal switch on ugate/lgate is low when shdna# = low for normal shutdown disabled enabled. ugate pulled low and lgate forced high if ovp detected ref 15 ? internal switch off ugate/lgate is low when shdna# = low enabled. disabled gnd 15 ? internal switch off ugate/lgate is low when shdna# = low disabled disabled ISL88550A
18 fn6168.0 october 12, 2005 figure 25. dual-mode feedback decoder setting the buck regulator output (v out ) with a resistive voltage-divider at fb the buck regulator output voltage can be adjusted from 0.7v to 3.5v using a resistiv e voltage-divider (figure 26). the ISL88550A regulates fb to a fixed reference voltage (0.7v). the adjusted output voltage is: where vfb is 0.7v and figure 26. setting v out wth a resistive voltage divider setting the vtt and vttr voltages (ldo) the termination power supply output (vtt) can be set by two different methods. firs t, the vtt output can be connected directly to the vtts input to force vtt to regulate to v refin /2. secondly, vtt can be forced to regulate higher than v refin /2 by connecting a resistive divider from vtt to vtts. the maximum value for vtt will be the v vtti - v dropout where v dropout = i vtt 0.3 typically. the termination reference voltage (vttr) will follow ? v refin . inductor selection (buck) the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 12a, v in = 12v, v out = 2.5v, ? sw = 300khz, 30% ripple current or lir = 0.3 find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): most inductor manufacturers provide inductors in standard values, such as 1.0h, 1.5h, 2.2h, 3.3h, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. input capacitor selection (buck) the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents: for most applications, non-tantalum chemistry capacitors (ceramic, aluminum, or oscon) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. if the ISL88550A are oper ated as the second stage of a two-stage power conversi on system, tantalum input capacitors are acceptable. in either configuration, choose a capacitor that has less than 10c temperature rise at the rms input current for optimal reliability and lifetime. fb 0.1 x ref (0.2v) 2.5v (fixed) 1.8v(fixed) out ref (2.0v) to error amplifier ISL88550A 2 v r r 1 v v ripple d c fb out + ? ? ? ? ? ? ? ? + = esr load ripple r i lir v = phase l fb r d r c c out out q2 gnd pgnd1 lgate ISL88550A ( ) () lir i f v v v v l max load sw in out in out ? = ( ) h 8 . 1 3 . 0 a 12 khz 300 v 12 v 5 . 2 v 12 v 5 . 2 l = ? = () ? ? ? ? ? ? ? ? + = 2 lir 1 i i max load peak ? ? ? ? ? ? ? ? ? = in out in out load rms v v 1 v v i i ISL88550A
19 fn6168.0 october 12, 2005 output capacitor selection (buck) the output filter capacitor must have low enough equivalent series resistance (r esr ) to meet output ripple and load- transient requirements, yet have high enough esr to satisfy stability requirements. for processor core voltage converters and other applications in which the output is subject to violent load transients, the output capacitor?s size depends on how much r esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in applications without large and fast load transients, the output capacitor?s size often depends on how much r esr is needed to maintain an acceptable level of output voltage ripple. the output ripple voltage of a step down controller is approximately equal to the total inductor ripple current multiplied by the output capacitor?s r esr . therefore, the maximum r esr required to meet ripple specifications is: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. t hus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tantalums, oscons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoo t requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transie nt response section). vtt output cap selection (ldo) place 2 x 10f 0805 ceramic capacitor as close to vtt output as possible for optimum performance of output loading up to +2.5a/-2.0a. in most applications, it is not necessary to add more capacitance. however, optional additional capacitances can be added further away (>1.5in) from vtt output. vttr output cap selection (ldo) the vttr buffer is a scaled down version of the vtt regulator, with much smaller output transconductance. its compensation cap can therefore be smaller, and its esr larger, than what is required for its larger counterpart. for typical applications requiring load current up to 20ma, a ceramic cap with a minimum value of 1f is recommended (esr<0.3 ? ). tie this cap between vttr and analog ground plane. vtti input cap selection (ldo) both the vtt and vttr output stages are powered from the same vtti input. their output voltages are referenced to the same refin input. the value of the vtti bypass cap is chosen to limit the amount of ripple/noise at vtti, or the amount of voltage dip during a load transient. typically, a ceramic cap of at least 10f should be used. this value is to be increased with larger load current, or if the trace from the vtti pin to the power source is long and has significant impedance. furthermore, to prevent undesirable vtti bounce from coupling back to the refin input and possibly causing instability in the loop, the refin pin should ideally tap its signal from a separate low impedance dc source rather than directly to the vtti input. if the latter is unavoidable, increase the amount of bypass at the vtti input and add additional bypass at the refin pin. mosfet selection (buck) the ISL88550A drive external, logic-level, n-channel mosfets as the circuit-switch elements. the key selection parameters: maximum drain-to-source voltage (v dss ): should be at least 20% higher than input supply rail at the high side mosfet?s drain. choose the mosfets with rated r ds(on) at v gs = 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet that has a conduction loss equal to switching loss at nominal input voltage and maximum output current (see below). for low-side mosfet, make sure that it does not spuriously turn on because of dv/dt caused by high-side mosfet turning on, as this would result in shoot through current degrading the efficiency. mosfets with a lower q gd to q gs ratio have higher immunity to dv/dt. for proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side mosfet, worst case is at v in(max) ; for high-side mosfet, it could be either at v in(min) or v in(max) ). the high-side mosfet and low-side mosfet have different loss components due to the circuit operation. the low-side mosfet operates as a zero voltage switch; therefore, major losses are 1. the channel conduction loss (p lscc ) 2. the body diode conduction loss (p lsdc ) 3. the gate-drive loss (p lsdr ) where v f is the body-diode forward-voltage drop, t dt is the dead time ( 30ns), and f sw is the switching frequency. () max load step esr i v r ? () lir i v r max load ripple esr () on ds 2 load in out lscc r i v v 1 p ? ? ? ? ? ? ? ? ? = sw dt f load lsdc f t v i 2 p = ISL88550A
20 fn6168.0 october 12, 2005 because of the zero-voltage sw itch operation, the low-side mosfet gate-drive loss occurs as a result of charging and discharging the input capacitance, (c iss ). this loss is distributed among the average lgate driver?s pull-up and pull-down resistance, r lgate (1 ? ), and the internal gate resistance (r gate ) of the mosfet (~2 ? ). the driver power dissipated is given by: the high-side mosf et operates as a duty-cycle control switch and has the following major losses: the channel conduction loss (p hscc ), the vi overlapping switching loss (p hssw ), and the drive loss (p hsdr ). the high-side mosfet does not have body-diode conduction loss because the diode never conducts current: use r ds(on) at t j(max) . where i gate is the average ugate driver output-current determined by: where r ugate is the high-side mosfet driver?s on- resistance (1.5 ? typical) and r gate is the internal gate resistance of the mosfet (~2 ? ): where v gs = v dd = 5v. in addition to the losses above, allow about 20% more for additional losses because of mosfet output capacitances and low-side mosfet body- diode reverse recovery charge dissipated in the high-side mosfet that is not well defined in the mosfet data sheet. refer to the mosfet data sheet for thermal-resistance specifications to calculate the pc board area needed to maintain the desired maximum operating junction temperature with the above-cal culated power dissipations. to reduce emi caused by swit ching noise, add a 0.1f ceramic capacitor from the high- side switch drain to the low- side switch source, or add resistors in series with ugate and lgate to slow down the switching transitions. adding series resistors increases the power dissipation of the mosfet, so ensure that this does not overheat the mosfet. mosfet snubber circuit (buck) fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at the switching nodes. this high-frequency ringing occurs at phase?s rising and falling transi tions and can interfere with circuit performance and generate emi. a series r-c snubber may be added across the lower mosfet to dampen this ringing. below is the procedure for selecting the value of the series r-c circuit: 1. connect a scope probe to measure phase to gnd, and observe the ringing frequency, ? r . 2. find the capacitor value (connected from phase to gnd) that reduces the ringing frequency by half. the circuit parasitic capacitance (c par ) at phase is then equal to 1/3 the value of the added capacitance above. the circuit parasitic inductance (l par ) is calculated by: the resistor for critical dampening (r snub ) is equal to 2 ? r x l par . adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. the capacitor (c snub ) should be at least 2 to 4 times the value of the c par in order to be effective. the power loss of the snubber circuit (p rsnub ) is dissipated in the resistor and can be calculated as: where v in is the input voltage and ? sw is the switching frequency. choose an r snub power rating that meets the specific application?s derating rule for the power dissipation calculated. setting the current limit (buck) the current-sense method used in the ISL88550A makes use of the on resistance (r ds(on) ) of the low side mosfet (q2 in typical application circuit). when calculating the current limit, use the wors t-case maximum value for r ds(on) from the mosfet data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each 1c of temperature rise. the minimum current-limit th reshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the valley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i lim(val) equals the minimum valley current-limit threshold voltage divided by the on resistance of q2 (r ds(on)q2 ). for the 50mv default setting, the minimum valley current-limit threshold is 40mv. connect ilim to av dd for a default 50mv valley current limit threshold. in adjustable mode, the valley current limit threshold is precisely 1/10th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to gnd with lgate gate gate sw 2 gs iss lsdr r r r f v c p + = () on ds 2 load in out hscc r i v v p = gate gd gs sw load in hssw i q q f i v p + = () gate ugate on gate r r v 5 . 2 i + = ugate gate gate sw gs g hsdr r r r f v q p + = () par 2 r par c f 2 1 l = sw 2 in snub rsnub f v c p = () ( ) () ? ? ? ? ? ? ? ? ? > 2 lir i i i max load max load val lim ISL88550A
21 fn6168.0 october 12, 2005 ilim connected to t he center tap. the external 250mv to 2v adjustment range corresponds to a 25mv to 200mv valley current-limit threshold. when ad justing the current limit, use 1% tolerance resistors and a divider current of approximately 10a to prevent significant inaccuracy in the valley current- limit tolerance. setting the foldback current limit (buck) alternately, foldback current lim it can be implemented if uvp is disabled. foldback current limit reduces the power dissipation of external components so they can withstand indefinite output overload or short circuit. with automatic recovery after the fault conditi on is removed. to implement foldback current limit, connect a resistor from v out to ilim (r1 in the typical application circuit), in addition to the resistor-divider network (r4 and r5) used for setting the adjustable current limit. the following is a procedure for calculating the values of r1, r4, and r5: 1. calculate the voltage, v ilim : 2. pick a percentage of foldback, p fb , from 15% to 40%. 3. calculate the voltage,v vilim(0v) , when the output is shorted (0v). figure 27. foldback current limit 4. the value of r4 can be calculated as: 5. the parallel combination of r1 and r5 is calculated as: 6. then r5 can be calculated as: 7. then r1 is calculated as: boost-supply capacitor selection (buck) the boost capacitor should be 0.1f to 4.7f, depending on the input and output voltages, external components, and pc board layout. the boost capacitance should be as large as possible to prevent it from ch arging to excessive voltage, but small enough to adequately charge during the minimum low- side mosfet conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). in addition, ensure that the boost capacitor does not discharge to below the minimum gate-to-source voltage required to keep the high-side mosfet fully enhanced for lowest on-resistance. this minimum gate to source voltage (v gs(min) ) is determined by: where v dd is 5v, q g is the total gate charge of the high-side mosfet, and c boost is the boost capacitor value where c boost is c7 in the typical application circuit. transient response (buck) the inductor ripple current also affects transient response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the output sag is also a function of the maximum duty factor, whic h can be calculated from the on-time and minimum off-time: where t off(min) is the minimum off-time (see the electrical characteristics) and k is from table 1. the overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: ) 2 q ( dson ) max ( load ilim r 2 lir 1 i 10 v ? ? ? ? ? ? ? = vddq ref ilim ISL88550A/ isl88551a r4 r5 c ref gnd r1 vddq ref ilim ISL88550A/ isl88551a r4 r5 c ref gnd r1 ISL88550A ilim fb ) v 0 ( ilim v p v = a 10 v v 2 4 r ) v 0 ( ilim ? = 4 r a 10 v 2 r 5 r // 1 r ? = () ()() [] 5 r // 1 r ) v 0 ( ilim ilim ) v 0 ( ilim ilim 5 r // 1 r r v v 4 r v v vddq r 4 r vddq 5 r ? ? ? ? = [] 5 r // 1 r 5 r // 1 r r 5 r r 5 r 1 r ? = () boost g dd min gs c q v v = () () () () ? ? ? ? ? ? + ? ? ? ? ? ? ? + ? = min off in out in out out min off in out 2 max load sag t v k v v v c 2 t v k v i l v () out out 2 max load soar v c 2 l i v ? = ISL88550A
22 fn6168.0 october 12, 2005 figure 28. typical ddr ii applications circuit 1f r3 r3 c3 150 220 ovp/uvp vdd vin boot ugate phase lgate pgnd1 out ilim ref fb refin vttr vin: 4.5v to 25v vddq 1.8v/12a q1 q2 - c8: 2x10f c11 12m c7 0.22f ISL88550A c5: 4.7f avdd ss ton skip# gnd stby# shdna# pok2 pok1 vtti vtt vtts pgnd2 1.5v c4 c6 c2 c12 150?f 12m avdd 100k 0.9v/10ma c1 c10 c13 1f c14 470f r4 200k r5 56.2k r1: 182k avdd q1 falco er1309 1.0uh, 35a, 2m c11 12m c7 1.5v c2 c12 220?f 12m avdd c9: open c10 0.22f c13 100k r3 r3 c3 220f ovp/uvp vdd vin boot ugate phase lgate pgnd1 out ilim ref fb refin vttr vin: 4.5v to 25v vddq 1.8v/12a q1 q2 c11 12m c7 ISL88550A 5v bias supply avdd ss ton skip# gnd stby# shdna# pok2 pok1 vtti vtt vtts pgnd2 1.5v c4 2x10f c6 1f c2 c12 150?f 12m avdd 0.9v/10ma c1 open c10 c13 q1: irf7821/30v/9m ? q2: irf7832/30v/5m ? c14 (optional) r4 avdd q1 l1: falco er1309 1.0h, 35a, 2m ? c11 12m ? c7 vtt: 0.9v1.5a 1.5v c2 10f c12 220f 12m ? avdd r2 c10 c13 ISL88550A
23 fn6168.0 october 12, 2005 figure 29. typical gfx application circuit applications information dropout performance (buck) the output voltage adjustable range for continuous conduction operation is restricted by the non-adjustable minimum off time one-shot. for best dropout performance, use the slower (200khz) on-time setting. when working with low input voltages, the duty-fac tor limit must be calculated using the worse case values for on and off times. manufacturing tolerances and internal propagation delays introduce an error to the t on k-factor. this error is greater at higher frequencies (see table 1). also, keep in mind that transient response performanc e of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor current ramps down during the minimum off-time (i down ) as much as it ramps up during the on-time (i up ). the ratio h=i up /i down indicates the controller?s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases, unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: 1f 100k r3 r3 c3 330f ovp/uvp vdd vin boot ugate phase lgate pgnd1 out ilim ref fb refin vttr vin: 4.5v to 25v gfxcore 0.95v/12a q1 q2 - c8: 2x10f c11 9m ? c7 0.22f ISL88550A 5v bias supply c5: 4.7f avdd ss ton skip# gnd stby# shdna# pok2 pok1 vtti vtt vtts pgnd2 1.8v c4 2x10f c6 1f c2 10f c12 9m ? avdd r2 100k 1v/10ma c10 0.22f c13 1f q1: irf7821/30v/9m ? q2: irf7832/30v/5m ? c14 470f (optional) r4 200k r5 56.2k r1: 182k q1 l1: falco er1309 1.0h, 35a, 2m ? c11 c7 pci-e 1.2v/2a c2 c12 330f avdd r2 100k c9: open c10 c13 r6 24.9k r7 69.8k r8 69.8k gpio gpio open : gfxcore = 0.95v gpio low : gfxcore = 1.20v r9 1.21k r10 4.99k () () 1 drop 2 drop min off 1 drop out min in v v k t h 1 v v v ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = ISL88550A
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6168.0 october 12, 2005 where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see the on- time one- shot (t on ) section), t off(min) is from the electrical characteristics, and k is taken from table 1. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. a dropout design example follows: ?v out = 2.5v ?f sw = 600khz ? k = 1.7s ?t off(min) = 450ns ?v drop1 = v drop2 = 100mv ?h = 1.5 pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attentio n. if possible, mount all of the power components on the topside of the board, with their ground terminals flush against one another. follow these guidelines for good pc board layout: ? keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be appr oached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. ? minimize current-sensing errors by connecting csp and csn directly across the current-sense resistor (r sense ). ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. fo r example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low side mosfet or between the inductor and the output filter capacitor. ? route high-speed switching nodes (boot, phase, ugate, and lgate) away fr om sensitive analog areas (ref, fb, and ilim). special layout considerations for ldo section the 20f output cap (or caps) at vtt should be placed as close to the vtt and pgnd2 pins (pins 12 and 11) as possible to minimize the series resistance/inductance in the trace. the pgnd2 side of the cap should be shorted with the lowest impedance path to the ground slug underneath the ic, which should also be star-connected to the gnd (pin 24) of the ic. a narrower trace can be used to tie the output voltage on the vtt side of the cap back to the vtts pin (pin 9). however, keep this trace well away from noisy signals such as the pgnd or pgnd2 to prevent noise from being injected into the error amplifier?s input. for best performance, the vtti bypass cap should also be placed as close to the vtti pin (pin 13) as possible. a short low impedance connection should also be made to tie the other side of the cap to the pgnd2 pin. the refin pin (pin 14) should be separately routed with a clean trace and adequately bypass to agnd. a suggested layout of the board can be found in evaluation board kit of ISL88550A. () v 3 . 4 v 1 . 0 v 1 . 0 s 7 . 1 ns 450 5 . 1 1 v 1 . 0 v 5 . 2 v min in = ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = ISL88550A
25 fn6168.0 october 12, 2005 ISL88550A thin quad flat no-lead plastic package (tqfn) thin micro lead frame plastic package (tmlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5b 28 lead quad flat no-lead plastic package (compliant to jedec mo-220whhd-1 issue i) symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - 0.02 0.05 - a2 - 0.55 0.80 9 a3 0.20 ref 9 b 0.20 0.25 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 3.15 3.25 3.35 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 3.15 3.25 3.35 7,8 e 0.50 bsc - k0.20 - - - l 0.50 0.55 0.60 8 n282 nd 7 3 ne 7 3 p- -0.609 --129 rev. 0 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation.

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